I. Field of the Disclosure
The technology of the disclosure relates generally to controlling voltage slew rates, and particularly to circuits that control the rate at which voltage is supplied to a load circuit.
II. Background
Processor-based systems employ voltage supply sources for providing voltage to various components for operation. Rather than coupling voltage supply sources directly to the components, a processor-based system may employ headswitch devices that distribute voltage from one or more voltage supply sources within the processor-based system. Notably, instead of continuously providing voltage to components within the processor-based system, headswitch devices can be provided and configured to provide voltage to corresponding power distribution networks within these components during active operation. In this manner, power consumption of a processor-based system may be reduced when components are not operating.
For example, to provide voltage to a processor core for powering the processor core, multiple headswitch devices are commonly disposed at locations on a processing system die around a perimeter of the processor core. Distributing the placement of headswitch devices strategically at locations around the perimeter of the processing core allows a supply voltage to be provided to multiple areas of the processor core with less complex wiring, as compared to providing the supply voltage from a single node. In this manner, the headswitch devices are configured to receive the supply voltage from one or more voltage supply sources. To control the distribution of the supply voltage from the headswitch devices distributed on the processing system die, the headswitch devices are configured to be controlled by control signals. The control signals are provided from the processor core to activate the headswitch devices to supply power to the power distribution network of the processor core.
However, prior to receiving the supply voltage from the headswitch devices, the processor core may be in an idle state, wherein voltage provided to the processor core may be reduced or collapsed to reduce power consumption. Thus, the voltage level of the corresponding power distribution network within the processor core may be approximately equal to zero Volts (0V). However, when the processor core transitions from an idle state to an active state, the processor core sends a control signal to the headswitch devices to increase the voltage provided to the processor core. Upon receiving the supply voltage from the voltage supply sources by way of the headswitch devices, the voltage of the processor core is raised from a lower voltage to the supply voltage in a substantially instantaneous manner. This fast voltage step may cause prolonged resonance within the power distribution network of the processor core. Notably, a processor core cannot operate until resonance on the corresponding power distribution network subsides. However, delaying operation of a processor core until resonance on the power distribution network subsides reduces the performance of the processor core.